1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of planarizing to remove a difference in height between a flash memory cell area and a logic device peripheral circuit area when forming a wordline of a non-volatile memory device in which a flash memory device and a logic device are merged.
2. Description of the Related Art
Semiconductor memory devices include RAM devices and ROM devices. In the RAM device, such as a DRAM (dynamic random access memory) and an SRAM (static random access memory), data are rapidly inputted/outputted into/from the RAM device and are volatilized as the lapse of time. On the contrary, the ROM device constantly maintains inputted data, but data are slowly inputted/outputted into/from the ROM device. Among those ROM devices, an EEPROM (electrically erasable and programmable ROM) capable of electrically inputting/outputting data and a flash memory device are widely used.
Further, conventionally, multiple semiconductor devices having different functions are merged in one chip due to the characteristics of manufacturers and demand on the users, thereby enhancing added value. For typical examples, there are a merged DRAM and logic (MDL) device including DRAM cells and logic devices and a merged flash and logic (MFL) device including flash memory cells and logic devices.
Generally, the programming of the flash memory cell is carried out by hot-electron injection into the floating gate. That is, an applied positive voltage on a control gate is coupled to a floating gate, so that electrons are captured in the floating gate through a tunnel oxide layer from a substrate. On the contrary, the erasing mechanism of the flash memory cell is Fowler-Nordheim (hereinafter, referred to as xe2x80x9cF-Nxe2x80x9d) tunneling off the floating gate to the drain region. That is, the electrons in the floating gate are transferred to the substrate by applying a negative voltage on the control gate. When a program is being executed, the ratio of coupled voltage on the floating gate due to the applied voltage on the control gate is the coupling ratio. As the coupling ratio becomes higher, the speed and performance of the device are enhanced.
In case of the MFL device, as the design rule decreases to less than 0.18 xcexcm, a split-gate structure in which a tip is formed on the edge area of the floating gate is used to increase the coupling ratio of the flash memory cell. By doing so, the erase efficiency and the program efficiency are improved to increase the coupling ratio.
In the flash memory cell with the split-gate structure, a wordline is formed using a conventional chemical mechanical polishing (hereinafter, referred to as xe2x80x9cCMP) process. So the whole chip should be planarized to uniformly form the wordline in a subsequent gate patterning process.
FIGS. 1A to 7B are sectional views illustrating a conventional method of forming a wordline in the split-gate type MFL device. Here, FIGS. 1A, 2A, 3A, 4A, 5A, 6A and 7A show a cell area in which a flash memory device is formed, and FIGS. 1B, 2B, 3B, 4B, 5B, 6B and 7B show a peripheral circuit area in which a logic device is formed.
Referring to FIGS. 1A and 1B, a first oxide layer 11 for forming a gate oxide layer (i.e., a tunnel oxide layer) of the flash memory device, a first polysilicon layer 13 for forming a floating gate and a nitride layer (not shown) are sequentially formed on a semiconductor substrate 10 such as a silicon substrate. Then, the nitride layer is patterned through a photolithography process to form a nitride layer pattern 16 defining a floating gate region. An oxide layer (not shown) is deposited on the nitride layer pattern 16 and the first polysilicon layer 13, and etched back to form spacers 18 on the sidewalls of the nitride layer pattern 16.
Using the spacer 18 as an etching mask, the first polysilicon layer 13 and the first oxide layer 11 are etched away. Through a typical ion-implantation process, a source region 20 is formed in the surface portion of the exposed substrate between the spacers 18. Then, after performing an oxidation process to cure silicon damage caused by the described etching process, a liner oxide layer (not shown) is deposited on the resultant structure and etched back to insulate the first polysilicon layer 13 from a source line that is to be formed in a subsequent process.
Referring to FIGS. 2A and 2B, a second polysilicon layer 21 is deposited on the resultant structure and planarized by a CMP or an etch-back process until the surface of the nitride layer pattern 16 is exposed. By doing so, the source line 22 connected to the source region 20 is formed so as to fill a gap between the spacers 18.
Referring to FIGS. 3A and 3B, after removing the nitride layer pattern 16 by a phosphoric acid stripping process, the first polysilicon layer 13 is dry-etched away using the spacers 18 as an etching mask. Then, after performing an oxidation process to cure silicon damage caused by the described etching process, the substrate is cleaned using HF. As a result, there is formed a floating gate structure 40 of the flash memory device including a gate oxide layer 12, two floating gates 14 separated by the spacers 18 and the source line 22 filling the gap between the spacers 18.
Referring to FIGS. 4A and 4B, a second oxide layer 23, a third polysilicon layer 25 for forming the wordline and the gate and a nitride layer 27 are sequentially formed on the entire surface of the substrate 10 including the floating gate structure 40. The second oxide layer 23 serves as a dielectric interlayer for insulating the floating gate from a control gate on the memory cell area and serves as a gate oxide layer of the logic device on the peripheral circuit area.
Referring to FIGS. 5A and 5B, the nitride layer 27 is removed by a CMP process until the surface of the floating gate structure 40, preferably the source line 22 is exposed, thereby planarizing the cell area and the peripheral circuit area. At this time, a nitride layer residue 28 remains on the part of the low step height.
Referring to FIGS. 6A and 6B, after selectively oxidizing the exposed surface of the third polysilicon layer 25 and the source line 22 to form an oxide layer 30, the nitride layer residue 28 is removed by a wet etching process. Then, through a photo process, a photoresist pattern 32 is formed to mask the cell area and to open a gate region of the peripheral circuit area.
Referring to FIGS. 7A and 7B, using the oxide layer 30 of the cell area and the photoresist pattern 32 of the peripheral circuit area as an etching mask, the exposed third polysilicon layer 25 is dry-etched away. By doing so, the wordline (i.e., the control gate) 26a of the flash memory device and the gate 26b of the logic device, which have a vertical profile, are simultaneously formed. Here, reference numeral 24a indicates the dielectric interlayer for insulating the control gate 26a from the floating gate 14 and reference numeral 24b indicates a gate oxide layer of the logic device.
At this time, the oxide layer 30 used as the etching mask is almost consumed during etching the third polysilicon layer 25 and is removed completely in a subsequent cleaning process and a pre-cleaning process for silicidation.
According to the described conventional method, since the basic height difference between the cell area and the peripheral circuit area exists already before performing the CMP process of FIG. 5, the CMP process should be sufficiently carried out to remove this step height. Therefore, due to the peripheral circuit area of the low height, the nitride layer 71 is removed completely on the edge of the cell area and the peripheral circuit area by the excessive CMP process, so that the formation of the wordline and the gate becomes impossible.
Further, when the wordline 26a is formed using the selectively oxidized oxide layer 30 as an etching mask, since no layer for preventing the etching is formed on the peripheral circuit area, the third conductive layer 25 of the peripheral circuit area is completely etched away if the photoresist pattern 32 is not formed. Accordingly, in order to form the wordline and the logic gate simultaneously, the photoresist pattern 32 for defining the gate pattern should be formed using a photo process. However, in the non-volatile memory device such as a MFL with a design rule of 0.1818 xcexcm and less, if the gate patterning is carried out without an anti-reflective layer, the variation of the gate linewidth becomes severe and the selectivity of the photoresist layer with respect to the underlying gate oxide layer becomes poor. Therefore, it is impossible to obtain the normal logic pattern.
In order to solve such problems, the present applicant invented a method of patterning a logic gate and a wordline simultaneously using a hard mask. This method is disclosed in Korean Patent Application No. 2001-9325. Hereinafter, this method will be described in detail with reference to the FIGS. 8A to 11B. FIGS. 8A, 9A and 10A show a cell area in which a flash memory device is formed, and FIGS. 8B, 9B and 10B show a peripheral circuit area in which a logic device is formed.
Referring to FIGS. 8A and 8B, a floating gate structure of the flash memory device including a gate oxide layer 52, two floating gates separated by oxide spacers 58 and a source line 62 connected to a source region 60 so as to fill a gap between the spacers 58 are formed on a semiconductor substrate 50 by the same methods as the methods described in FIGS. 1A to 3B. Then, an oxide layer 63, a polysilicon layer 65 for a gate, an anti-reflective layer 67 consisting of a SiN or a SiON and a hard mask layer consisting of a CVD-oxide are sequentially formed on the entire surface of the resultant structure.
Referring to FIGS. 9A and 9B, after removing the hard mask layer 69 and the anti-reflective layer 67 of the cell area by a photolithography process, a nitride layer is formed on the entire surface of the resultant structure. By doing so, a hard mask layer residue 70 and an anti-reflective layer residue 68 remain over the polysilicon layer 65 of the peripheral circuit area.
Referring to FIGS. 10A and 10B, the nitride layer 71 is removed by a CMP process until the source line 62 is exposed, thereby planarizing the cell area and the peripheral circuit area. That is, the planarization process is carried out so that the polysilicon layer 65 remains on the cell area while the nitride layer 71 remains on the peripheral circuit area. At this time, a nitride layer residue 72 remains on the cell area having a low step height.
Referring to FIGS. 11A and 11B, after selectively oxidizing the exposed surfaces of the polysilicon layer 65 and the source line 62 to form an oxide layer 74, the nitride layer residue 72 is removed by a wet etching process. Then, through a photo process, a photoresist pattern 76 is formed so as to mask the cell area and to open the gate region of the peripheral circuit area. Using the photoresist pattern 76 as an etching mask, the hard mask layer 70 and the anti-reflective layer 68 are dry-etched away to form a hard mask layer pattern 70a and an anti-reflective layer pattern 68a. 
Though not shown, after removing the photoresist pattern 76 by ashing and stripping processes, the exposed polysilicon layer 65 is dry-etched away using the oxide layer 74 of the cell area and the hard mask layer pattern 70a of the peripheral circuit area as an etching mask, to thereby form a wordline (i.e., a control gate) of the flash memory device and a gate of the logic device simultaneously.
According to the above-described conventional method, the-diffused reflection of light is prevented since the gate patterning is carried out using the anti-reflective layer, so that the gate linewidth can be formed uniformly. Further, the hard mask layer for securing the selectivity with respect to the underlying gate oxide layer is used to form the normal logic pattern.
However, since the basic difference in height between the cell area and the peripheral area exists already before performing the CMP process to the nitride layer 71, the CMP process is performed excessively to the polysilicon layer 65 on the edge of the cell area and the peripheral circuit area due to the peripheral circuit area of the low height. As a result, it is impossible to form the wordline and the gate on the edge of the cell area and the peripheral circuit area.
Therefore, in order to form a wordline of a non-volatile memory device in which a flash memory device and a logic device are combined, it is a first object of the present invention to provide a planarizing method for removing the height difference between a cell area of the flash memory device and a peripheral circuit area of the logic device.
It is a second object of the present invention to provide a method of planarizing a semiconductor device in which a stacked structure is formed only on a predetermined region.
In accordance with the present invention, there is provided a method of manufacturing a non-volatile memory device in which a flash memory device is formed on a cell area of a semiconductor substrate and a logic device is formed on a peripheral area. The method comprises the steps of forming a floating gate structure on the cell area of the semiconductor substrate; forming a conductive layer on the floating gate structure and the semiconductor substrate; forming a hard mask layer on the conductive layer; forming a first insulating layer on the hard mask layer; removing the first insulating layer of the cell area to leave the first insulating layer pattern on the peripheral circuit area; removing the hard mask layer of the cell area; forming a second insulating layer on the conductive layer and the first insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area; planarizing the cell area and the peripheral circuit area by removing the second insulating layer and the first insulating layer pattern until the floating gate structure is exposed; and patterning the conductive layer to form wordlines on both sidewalls of the floating gate structure and simultaneously to form a gate of the logic device on the peripheral circuit area.
In accordance with a second aspect of the present invention, there is provided a method of planarizing a semiconductor device comprising the steps of forming a conductive layer on the surface of a semiconductor substrate having a first area in which a stacked structure is formed and a second area in which the stacked structure is not formed; forming a hard mask layer on the conductive layer; forming a first insulating layer on the hard mask layer; removing the first insulating layer on the first area to leave the first insulating layer pattern only on the first area; removing the hard mask layer on the first area; forming a second insulating layer so as to be stacked on the conductive layer of the first area and on the first insulating layer pattern of the second area, thereby removing a height difference between the first area and the second area; and thereby planarizing the first area and the second area by removing the second insulating layer and the first insulating layer pattern until the stacked structure is exposed.
According to the present invention, after removing the first insulating layer of the cell area having a high step height, the second insulating layer is deposited so that the insulating layer of the peripheral circuit area having a low step height is heightened to the height of the cell. Therefore, when the CMP process of forming the wordline is carried out, excessive polishing of the cell area adjacent to the peripheral circuit can be prevented as compared to the cell area located far away from the peripheral circuit area.
Also, since the hard mask layer for patterning the gate remains on the peripheral circuit area after an oxide layer for forming the wordline is selectively formed, the wordline and the gate of the logic device can be patterned at the same time. Further, the gate linewidth can be formed uniformly using an anti-reflective layer, and the hard mask layer having the high selectivity with respect to the underlying gate oxide layer is used to obtain the normal logic pattern.
Furthermore, the doping level of the memory cell wordline is differentiated from that of the logic device gate such that only wordline is selectively doped with a high concentration. Thus, during reading the cell, a depletion layer of the wordline can be reduced.
These and other features of the present invention will be readily apparent to those of ordinary skill in the art upon review of the detailed description that follows.